The de-multiplexer is the inverse of the multiplexer, in that it takes a single data input and n address inputs. It has 2n outputs. The address input determine which data output is going to have the same value as the data input. The other data outputs will have the value 0.
Featured post
Transaction Recording In Verilog Or System Verilog
As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transac...

Friday, 26 February 2010
Subscribe to:
Post Comments (Atom)
-
Today India is home to some of the finest semiconductor companies in the world. The semiconductor companies in India are reputed across t...
-
Q1: What is UVM? What is the advantage of UVM? Ans: UVM (Universal Verification Methodology) is a standardized methodology for verify...
-
1. 8-bit Micro Processor 2. RISC Processor in VLDH 3. Floating Point Unit 4. LFSR - Random Number Generator 5. Versatile Counter 6. ...
-
There is a special Coding style for State Machines in VHDL as well as in Verilog. Let us consider below given state machine which is a “10...
-
Design 1: Design 2:

No comments:
Post a comment
Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.