VHDL code for AND gate


library ieee;
use ieee.std_logic_1164.all;

entity my_and is

  port (a, b : in  std_logic;
        c    : out std_logic);

end my_and;

architecture my_and_arc of my_and is

  c <= a and b;

end my_and_arc;

Positive and Negative Edge Detector Circuit

Positive and negative edge detection is a common requirement in microprocessors. One application could be to detect edge/level triggered events on certain GPIO inputs. Here i will show you a simple circuit which is use to detect Positive as well negative edges.


library ieee;
use ieee.std_logic_1164.all;
entity edge is
   port (
    inp        : in  std_logic;         -- inpit
    clk        : in  std_logic;         -- clock
    rst        : in  std_logic;         -- reset
    edge_op : out std_logic);        -- setected edge output
 end edge;

architecture edge_ar of edge is
  signal sig1 : std_logic;              -- signal from 1st flop
  signal sig2 : std_logic;              -- signal from 2nd flop

begin  -- edge_ar
   edge : process(clk, rst)
    if rst = '1' then
      sig1 <= '0';
      sig2 <= '0';
    elsif clk'event and clk = '1' then
      sig1 <= inp;
      sig2 <= sig1;
    end if;
  end process edge;

  edge_op <= sig1 xor sig2;

end edge_ar;

What is Clock Skew?

Given two sequentially-adjacent registers, Ri and Rj, and an equipotential clock distribution network, the clock skew between these two registers is defined as

Tskew-i,j = Tci - Tcj

where Tci and Tcj are the clock delays from the clock source to the registers Ri and Rj, respectively.

ASIC Implementation Design Cycle

Following diagram shows the basic flow of the complete HDL Implementation design cycle.

FPGA Implementation Design Cycle

Following diagram shows the basic flow of the complete HDL Implementation design cycle.

Netgen - The Circuit Netlist Comparison (LVS) and Netlist Conversion Tool

Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.

Netgen version 1.3 is the stable branch and has been essentially unchanged for several years. The development branch version 1.4 is an attempt to bring netgen up to par with the industry-standard Calibre tool from Mentor Graphics. Since (as far as I know) all LVS tools are based on the same class partitioning algorithm, this effort is not as difficult as it may seem. Mostly, netgen must be made to properly understand hierarchy, device properties, and generate a more readable output. All these changes are now underway (as of November 2007, when the development version 1.4 branch was created).

Netgen was developed independently of magic, written by Massimo Sivilotti, and eventually incorporated into the beginnings of the Tanner L-Edit suite of tools. However, the original code was left open source, and so I have incorporated it into the Tcl-based suite of tools including magic, IRSIM, and xcircuit.


IRSIM - tThe Switch-level Digital Circuit Simulator.

IRSIM is a tool for simulating digital circuits. It is a "switch-level" simulator; that is, it treats transistors as ideal switches. Extracted capacitance and lumped resistance values are used to make the switch a little bit more realistic than the ideal, using the RC time constants to predict the relative timing of events.

IRSIM shares a history with magic, although it is an independent program. Magic was designed to produce, and IRSIM to read, the ".sim" file format, which is largely unused outside of these two programs. IRSIM was developed at Stanford, while Magic was developed at Berkeley. Parts of Magic were developed especially for use with IRSIM, allowing IRSIM to run a simulation in the "background" (i.e., a forked process communicating through a pipe), while displaying information about the values of signals directly on the VLSI layout.

For "quick" simulations of digital circuits, IRSIM is still quite useful for confirming basic operation of digital circuit layouts. The addition of scheduling commands ("at", "every", "when", and "whenever") put IRSIM into the same class as Verilog simulators. It is, in my opinion, much easier to write complicated testbench simulations using Tcl and IRSIM. I have used IRSIM to validate the digital parts of several production chips at MultiGiG, including the simulation of analog behavior such as PLL locking.

IRSIM version 9.5 was a long-standing and stable version that corresponded to the relatively stable Magic version 6.5. When magic was recast in a Tcl/Tk interpreter framework (versions 7.2 and 7.3), IRSIM could no longer operate as a background process. However, it was clear that if IRSIM could also be recast in the same Tcl/Tk interpreter framework, the level of interaction between it and Magic would be greatly increased.

I set about to create the "new" IRSIM, although it came along in fits and starts as I had time to work on it. Because the original "analyzer" graphic display window (and GUI, to a very limited extent) was written in Xt (the rather primitive window system that is an integral part of X11), it was scrapped for a while. In its place, I substituted graphs in "Blt" based on the same in "tclspice" (see SourceForge for the tclspice project). Unfortunately, "Blt" insists that all data vectors must be real-valued, which is 1) a severe waste of space for binary digital values, and 2) is unable to represent the concept of an "unknown" value that is so crucial to fast switch simulation. So, eventually I was forced to scrap BLT and actually sit down and code out a real Tcl-based analyzer window and GUI. The result is finally done in revision 9.7.3.


XCircuit - The Circuit Drawing and Schematic Capture Tool

There are drawing programs, and there are schematic capture programs. All schematic capture programs will produce output for inclusion in publications. However, these programs have different goals, and it shows. Rarely is the output of a schematic capture program really suitable for publication; often it is not even readable, or cannot be scaled. Engineers who really want to have a useful schematic drawing of a circuit usually redraw the circuit in a general drawing program, which can be both tedious and prone to introducing new errors.

XCircuit is a UNIX/X11 (and Windows, if you have an X-Server running, or Windows API, if not) program for drawing publishable-quality electrical circuit schematic diagrams and related figures, and produce circuit netlists through schematic capture. XCircuit regards circuits as inherently hierarchical, and writes both hierarchical PostScript output and hierarchical SPICE netlists. Circuit components are saved in and retrieved from libraries which are fully editable. XCircuit does not separate artistic expression from circuit drawing; it maintains flexiblity in style without compromising the power of schematic capture.


Magic - The VLSI Layout Editor, Extraction, and DRC Tool.

Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

Xilinx ISE Design suite 10.1

Xilinx Integrated Software Environment (ISE) is a powerful yet flexible integrated design environment that allows you to design Xilinx FPGA and CPLD devices from start to finish. ISE includes our world class design entry, synthesis and implementation tools delivering the industry's fastest place and route times, highest performance, and most advanced design methodologies.
Project Navigator is the user interface that helps you manage the entire design process including design entry, simulation, synthesis, implementation and finally download the configuration of your FPGA or CPLD device.
The following is an outline of the features offered in ISE.

Design Entry

  • HDL Editor
  • StateCAD State Machine Editor
  • Schematic Editor - Engineering Capture System (ECS)
  • CORE Generator


  • XST - Xilinx Synthesis Technology
  • Integration with LeonardoSpectrum from Mentor Graphics, Inc.
  • Integration with Synplify from Synplicity, Inc.


  • HDL Bencher Testbench Generator
  • Integration with ModelSim Simulator from Model Technology, Inc.


  • Translate
  • MAP
  • Place and Route (PAR)
  • Floorplanner
  • FPGA Editor
  • Timing Analyzer
  • XPower
  • Fit (CPLD only)
  • Chipviewer (CPLD only)

Device Download and Program File Formatting

  • BitGen
  • iMPACT

Download the Xilinx ISE 10.1 design suit from Here

Transaction Layer (TL) of PCI Express

This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions. On the transmit side, the Transaction Layer receives request data (such as “read from BIOS location FFF0h”) or completion data (“here is the result of that read”) from the device core, and then turns that information into an outgoing PCI Express transaction. On the receive side, the Transaction Layer also accepts incoming PCI Express transactions from its Data Link Layer (refer to fig.). This layer assumes all incoming information is correct, because it relies on its Data Link Layer to ensure that all incoming information is error-free and properly ordered.

AMD and Intel Announce Settlement of All Antitrust and IP Disputes

Intel Corporation and Advanced Micro Devices (NYSE: AMD) today announced a comprehensive agreement to end all outstanding legal disputes between the companies, including antitrust litigation and patent cross license disputes.
In a joint statement the two companies commented, "While the relationship between the two companies has been difficult in the past, this agreement ends the legal disputes and enables the companies to focus all of our efforts on product innovation and development."
Under terms of the agreement, AMD and Intel obtain patent rights from a new 5-year cross license agreement, Intel and AMD will give up any claims of breach from the previous license agreement, and Intel will pay AMD $1.25 billion. Intel has also agreed to abide by a set of business practice provisions. As a result, AMD will drop all pending litigation including the case in U.S. District Court in Delaware and two cases pending in Japan. AMD will also withdraw all of its regulatory complaints worldwide. The agreement will be made public in filings with the Securities and Exchange Commission.

ELECTRIC VLSI Design Software

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:

  • Custom IC Layout
  • Schematic Capture (Digital and Analog)
  • Textual Languages such as VHDL and Verilog
  • ....and much more.

The Electric VLSI Design System is a highly flexible and powerful system that can handle many different types of circuit design (MOS, Bipolar, schematics, printed circuitry, hardware description languages, etc.) It handles geometry at any angle (not just Manhattan) and can even handle curves.

Layout is done by placing and wiring electrical components. Although this is standard practice for schematics, it is unusual for chip layout. However, because of this style of design, Electric understands chip layout at a more sophisticated level, and can aid in design to an unprecedented degree.

Electric has many analysis tools, including design-rule checking, simulation, and network comparison. Electric has many synthesis tools, including routing, compaction, silicon compilation, PLA generation, and compensation.

The user interface is quite sophisticated and runs on all popular workstations (Windows, Macintosh, and UNIX). It also provides interpretive languages for advanced users.

The software is freely available at www.staticfreesoft.com

VLSI Interview Questions-1

  1. what is the difference between mealy and moore state-machines
  2. how to solve setup and hold violations in the design
  3. what is antenna violation & ways to prevent it
  4. we have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage
  5. what is tie-high and tie-low cells and where it is used
  6. what is the difference between latches and flip-flops based designs
  7. what is High-Vt and Low Vt cells
  8. what is LEF mean?
  9. what is DEF mean?
  10. steps involved in designing an optimal padring
  11. what is metastability and steps to prevent it
  12. what is local-skew, global skew and useful skew
  13. what are the various timing-paths which i should take care in my STA runs?
  14. what are the various components of leakage-power
  15. what are the various yield losses in the design
  16. what is meant by virtual clock definition and why do i need it
  17. what are the various variations which impacts timing of the design
  18. what are the various Design constraints used, while performing synthesis for a design
  19. specify few verilog constructs which are not supported by the synthesis tool
  20. what are the various capacitances with an MOSFET?
  21. Vds-Ids curve for an MOSFET, with increasing Vgs
  22. explain basic operation of an MOSFET
  23. what is channel length modulation
  24. what is body effect
  25. what is latchup in CMOS design and ways to prevent it?
  26. what are the various design changes you do to meet design power targets
  27. what is meant by library characterization
  28. what is meant by wireload model
  29. what are the measures to be taken to design for optimized area
  30. what all will you be thinking while performing floorplan
  31. what are the measures in the design taken for meeting signal integrity targets
  32. what are the measures taken in the Design achieving better yield
  33. what are the measures or precautions to be taken in the design when the chip has both analog and digital portions.
  34. what are the steps incorporated for Engineering Change order[ECO]
  35. what are the steps performed to achieve Lithography friendly Design
  36. what does synthesis mean?
  37. what are the pre-requistes to perform synthesis
  38. can you explain the synthesis flow
  39. what are the various ways to reduce clock insertion delay in the design
  40. what are the various functional verification methodologies
  41. what does formal verification mean
  42. how will you time the output path in STA
  43. how will you time the input path in STA
  44. what is false path mean in STA and in what scenarios falsepath can come
  45. what does multicycle path mean in STA and in what scenarios MCP can come
  46. what are source synchronous paths in STA
  47. Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it.
  48. we have multiple instances in RTL, do you do anything special during synthesis stage
  49. what do you call an event and when do you call an assertion.
  50. what is difference between FPGA and ASIC.
Solutions to these questions will be provided on request.

A typical analog design flow

In case of analog design, the flow changes somewhat.

=>Specifications=> Architecture =>Circuit Design =>SPICE Simulation =>Layout =>Parametric Extraction / Back Annotation =>Final Design =>Tape Out to foundry.

While digital design is highly automated now, very small portion of analog design can be automated. There is a hardware description language called AHDL but is not widely used as it does not accurately give us the behavioral model of the circuit because of the complexity of the effects of parasitic on the analog behavior of the circuit. Many analog chips are what are termed as “flat” or non-hierarchical designs. This is true for small transistor count chips such as an operational amplifier, or a filter or a power management chip. For more complex analog chips such as data converters, the design is done at a transistor level, building up to a cell level, then a block level and then integrated at a chip level. Not many CAD tools are available for analog design even today and thus analog design remains a difficult art. SPICE remains the most useful simulation tool for analog as well as digital design.

From above discussion n from my personal experience i feel that digital design is the most important aspect of the VLSI design flow. Think if your design has some bug...!! the whole process then is costing billions of $. So it's very essential to take care start from the initial phase of designing.

Here during our discussion further we will go through several important concepts of digital dsigning and also see some standard designs.

A typical digital design flow

Specification =>Architecture =>RTL Coding =>RTL Verification =>Synthesis =>Backend =>Tape Out to Foundry to get end product….a wafer with repeated number of identical Ics.

All modern digital designs start with a designer writing a hardware description of the IC (using HDL or Hardware Description Language) in Verilog/VHDL. A Verilog or VHDL program essentially describes the hardware (logic gates, Flip-Flops, counters etc) and the interconnect of the circuit blocks and the functionality. Various CAD tools are available to synthesize a circuit based on the HDL. The most widely used synthesis tools come from two CAD companies, Synposys and Cadence.

Without going into details, we can say that the VHDL can be called as the "C" of the VLSI industry. VHDL stands for "VHSIC Hardware Definition Language", where VHSIC stands for "Very High Speed Integrated Circuit". This language is used to design the circuits at a high-level, in two ways. It can either be a behavioral description, which describes what the circuit is supposed to do, or a structural description, which describes what the circuit is made of. There are other languages for describing circuits, such as Verilog, which work in a similar fashion.

Both forms of description are then used to generate a very low-level description that actually spells out how all this is to be fabricated on the silicon chips. This will result in the manufacture of the intended IC.


The de-multiplexer is the inverse of the multiplexer, in that it takes a single data input and n address inputs. It has 2n outputs. The address input determine which data output is going to have the same value as the data input. The other data outputs will have the value 0.


Just opposite to decoder an encoder has many inputs but less outputs.
Below figure shows an example of 4-to-2 Encoder 


A multiplexer performs the function of selecting the input on any one of 'n' input lines and feeding this input to one output line.

Assume that we have four lines, C0C1C2 and C3, which are to be multiplexed on a single line, Output (f). The four input lines are also known as the Data Inputs. Since there are four inputs, we will need two additional inputs to the multiplexer, known as the Select Inputs, to select which of the C inputs is to appear at the output. Call these select lines A and B.
The gate implementation of a 4-line to 1-line multiplexer is shown below:

Xilinx Virtex-6 FPGA Family Achieves Full Production Qualification on UMC’s High-Performance 40nm

UMC, a leading global semiconductor foundry, and Xilinx Inc. (XLNX) today announced they have fully qualified the Virtex(R)-6 FPGA family on the foundry's high- performance 40nm logic process. The qualification is the result of the close work between engineering teams from both companies to further enhance yield, reliability and cycle time. The full qualification of the Virtex-6 family signifies the transition to 40nm volume production following UMC's first shipments of the devices in March 2009.
"We highly value the ongoing execution of our long time manufacturing partner UMC," said Xilinx CEOMoshe Gavrielov. "We have collaborated together to deliver several generations of industry leading FPGA families."
"This 40nm achievement follows a long history of successful product family launches with Xilinx," said UMC CEO Dr. Shih-Wei Sun. "Today's production readiness of the 40nm Virtex-6 family underscores our ongoing commitment to Xilinx and our long-term partnership."
Built using third-generation Xilinx ASMBL(TM) architecture, the Virtex-6 FPGA family delivers 15% higher performance and 15% lower power consumption compared to competitive 40nm FPGA offerings. The devices operate on a 1.0v core voltage with an available 0.9v low-power option and are supported by a new generation of development tools delivered by ISE(R) Design Suite 11 and a vast library of IP already available for the market leading 65-nm Virtex-5 FPGA family to ensure productive development and design migration.
"Reaching the production milestone means we have stable and predictable yields that allow us to meet our growing customer demands reliably," said Vincent Tong, Xilinx Senior Vice President, New Product Introductions and Worldwide Quality. "This would not be possible without the joint collaboration with UMC where we used Xilinx's next generation FPGA diagnostic tools along with UMC's rapid info-turn yield learning vehicles to achieve significant yield and quality improvement of 40nm."
Early engagement, design for manufacturing and an effective test vehicle process are also contributing to the successful roll-out of the Virtex-6 family. By building on what they learned from working together closely on previous generations, the Xilinx and UMC engineering teams were able to beat the tape-out to production duration of the Virtex-5 family by a quarter, Tong noted.
"The successful qualification of Virtex-6 is the result of the close teamwork between Xilinx and UMC engineers to address the challenges of 40nm high performance technology," said S.C. Chien, Vice President of Advanced Technology Development at UMC. "UMC dedicated significant engineering talent and resources in our joint effort with Xilinx, such as customizing device specifications to their product specifications, delivering DFM for stable yield, fast info-turn vehicle to enhance quality, and quick diagnosis methodology. We are excited to see that our teamwork has paid off with today's milestone."
UMC's independently developed 45/40nm logic process utilizes sophisticated immersion lithography for its 12 critical layers and incorporates the latest technology advancements such as ultra-shallow junction, embedded silicon- germanium and mobility enhancement techniques, and ultra low-k dielectrics. Currently, several customers have 45/40nm products being manufactured at UMC, with thousands of wafers having already been shipped.
Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. The Virtex-6 FPGA family comprises three domain-optimized FPGA platforms that deliver different feature mixes, including DSP slices, memory blocks and serial transceivers supporting up to 11.2Gb/s to best address a variety of customer applications. Currently, six out of nine Virtex-6 family base devices are shipping. All nine are scheduled to be available in production volumes by the end of the second quarter of CY2010.
About UMC
UMC ( UMC, TSE: 2303) is a leading global semiconductor foundry that provides advanced technology and manufacturing services for applications spanning every major sector of the IC industry. UMC's customer-driven foundry solutions allow chip designers to leverage the strength of the company's leading-edge processes, which include production proven 65nm, 45/40nm, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 12,000 people worldwide and has offices in TaiwanJapanSingaporeEurope, and the United States. UMC can be found on the web athttp://www.umc.com .
About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visithttp://www.xilinx.com/ .
XILINX, the Xilinx Logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.


Decoder is a multiple input; multiple output logic circuit that converts coded inputs in coded outputs, where input and output codes are different.

Inputs have fewer inputs than output. Below is a simple example of 2-to-4 decoder.

Popular Posts