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Friday, 19 June 2009


PCI Express has generated a lot of excitement in the PC enthusiast scene in a short amount of time. And with good reason, since it promises to rid the PC of its bandwidth woes and enable a new class of applications.

Conceptually, the PCIe bus can be thought of as a high-speed serial replacement of the older (parallel) PCI/PCI-X bus. At the software-level, PCIe preserves compatibility with PCI; a PCIe device can be configured and used in legacy applications and operating-systems which have no direct knowledge of PCIe's newer features. In terms of bus-protocol, PCIe communication is encapsulated in packets.
As shown in Figure , PCI Express unifies the I/O system using a common bus architecture. In addition, PCI Express replaces some of the internal buses that link subsystems.

This third-generation I/O technology is needed today since PCI-based shared, parallel-bus-signaling technology is approaching its practical performance limits; it is increasingly difficult to scale-up bandwidth just by increasing the number of signal lines. More signal lines mean difficult clock-to-data skew management, creating complex PCB layout rules that make cost-effective implementations in the FR4 (current copper PCB) technology difficult. In addition, increasing the number of signal lines also increases the power dissipation. PCI Express allows for very high available bandwidth per pin with the ability to cost-effectively scale towards the 12 GHz limits of copper signaling technology.

PCI Express is designed to be a general-purpose serial I/O interconnect that can be used in multiple market segments, including desktop, mobile, server, storage and embedded communications. PCI Express can be used as a peripheral device interconnect, a chip-to-chip interconnect, and a bridge to other interconnects like 1394b, USB2.0, InifiniBand™ and Ethernet. It can also be used in graphics chipsets for increased graphics bandwidth.

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